SJ 20073-1992 Detailed specification for semiconductor integrated circuit Jμ8254 type programmable timer counter

This specification specifies the detailed requirements for the semiconductor integrated circuit Jμ8254 type programmable timer counter (hereinafter referred to as the device). This specification applies to the development, production and procurement of the device. SJ 20073-1992 Semiconductor Integrated Circuit Jμ8254 Type Programmable Timer Counter Detailed Specification SJ20073-1992 Standard Download Decompression Password: www.bzxz.net

Military Standard of the Electronic Industry of the People's Republic of China SJ20073-92
Semiconductor Integrated Circuits
Ju8254 Programmable Timer Counter
Detailed Specification
Published on November 19, 1992
Implementation on May 1, 1993
Published by the Ministry of Machinery and Electronics Industry of the People's Republic of China 1 Scope
1.1 Subject Content·
1.2 Scope of Application
1.3 Classification
Referenced Documents
3 Requirements
Detailed Requirements·
3.2 Design, Structure and Dimensions
Lead Materials and Coating
Electrical Characteristics
Electrical Test Requirements…
3.6 Standards·
3.7 Classification of Microcircuit Groups
4 Quality Assurance Provisions
Sampling 4.2 Sampling and inspection
4.3 Identification inspection
4.4 Quality consistency inspection
4.5 Inspection method
5 Delivery preparation
5.1 Packaging requirements
6 Notes
6.1 General provisions on test loss
Ordering information
6.3 Functional description, symbols and definitions
Substitution
IKAONKAa-
People's Republic of China Electronic Industry Military Standard Semiconductor integrated circuits
Ju8254 type programmable timer counter Detailed specification 1 Scope
1.1 Main content
SJ20073—92
This specification specifies the detailed requirements for long conductor integrated circuit J8254 type programmable timer counter (hereinafter referred to as the device).
1.2 Scope of Application
This specification applies to the development, production and procurement of devices. 1.3 Classification
This specification classifies microcircuits according to device model, device level, packaging form, rated value and recommended operating conditions. 1.3.1 Device Number
The device number shall comply with the provisions of Article 3.6.2 of GJB597 "General Specification for Microcircuits" 1.3.1.1 Device Model
The device model is as follows:
Device Model
Ju8254
1.3.t.2 Device Level
Part Name
Programmable Timer Counter
The device level is Class B as specified in Article 3.4 of G.IB597 and Class B1 as specified in this specification. The clauses in this specification that provide additional explanations for Class B1 should be understood as the same as Class B. 1.3.1.3 Package form The package forms are as follows: Package form 1 D24L3 (24-lead ceramic effect series package) C28P3 (ceramic leadless chip carrier package): 1) According to GB70922 "Conductor Collector Circuit Outline Dimensions". 1.3.2 Absolute circuit ratings
The absolute maximum rated values ​​are as follows:
Promulgated by the Ministry of Machinery and Electronics Industry of the People's Republic of China on November 19, 1992 and implemented on May 1, 1993
Any output terminal relative to the Ys terminal
Storage temperature range
Lead soldering temperature (5s)
Junction temperature (Ts=125°C)
1.3.3 Recommended operating conditions
The recommended operating conditions are as follows:
Power supply voltage
Input high level voltage
Input low level ground voltage
Operating frequency
Case operating temperature range
Clock rise time
Time and fall time
Referenced documents
s# 20073--92
GB3431.1—82Semiconductor integrated circuit text symbolsElectrical parameter text symbolsGB3431.2—86Flat conductor integrated circuit text symbolsFunction symbols of lead terminalsGB4590--84Mechanical and climatic test methods for semiconductor integrated circuitsGB7092—93Dimensions of semiconductor integrated circuitsGJB548--88Test methods and procedures for microelectronic devicesGJB597—88General specification for microcircuits
GJB/Z105Electronic product anti-static discharge control manual3Requirements
3.1Detailed requirements
All requirements shall comply with the provisions of GJB597 and this specification. 3.2Design, structure and dimensions
The design, structure and dimensions shall comply with the provisions of GJB597 and this specification. 3.2.1 Terminal arrangement
The terminal arrangement shall comply with the provisions of Figure 1: The terminal arrangement is a diagram, 2
HTTKAONKAca-
SJ 20073---92
E3EGATE2
Compared to the carrier package terminal arrangement
OCT010
Vss port
Dual row package terminal arrangement
Figure 1 Terminal arrangement
3.2.2 Functional block diagram
The functional block diagram shall comply with the provisions of Figure 2.
Data bus
Buffer
Control word
Register
Figure 2 Functional block diagram
3.2.3 Functional description, symbols and definitions
Counter
Counter
Counter
Functional description, symbols and definitions shall comply with the provisions of Article 6.3 of this specification. 3.2.4 Package form
The package form shall comply with the provisions of Article 1.3.1.3 of this specification. 3.3 Lead material and coating
Lead material and coating shall comply with the provisions of Article 3.5.6 of GJB597. 3.4 Electrical characteristics
SJ20073-92
Electrical characteristics shall comply with the provisions of Table 1, or no other provisions, suitable for the full operating temperature range. 3.5 Electrical test requirements
Electrical test requirements for each level of devices shall be the relevant groups specified in Table 2, and the electrical tests of each group shall be in accordance with the provisions of Table 3.
3.6 Marking
Marking shall comply with the provisions of Article 3.6 of GJB597. Division of microcircuit groups
The devices involved in this specification are the 107th microcircuit group (see Appendix E of GJB597). Table
Electrical characteristics
Serial number! ）
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Input load current
Output three-state leakage current
(only 0-~D7)
Power supply current
Input capacitance
Input/output capacitance
Address setup before RDI
Isu AV-RL)
Cstsu before RD (CSL-RI)
Address hold after RDT
RD pulse width
Delay time
(starting from RDI)
Th(RJ-AV)
L(RL-DV)
Condition 2)
IoL = 2.0 mA
Fon = -400 μA
=Vm to ov
Yo=Vop to 0.45V
fep-1 MH2, Te-25 °C.
Te=25 °C, Vp-0 V, not
tested Carbon connected to Vs5
Yor=0.8 V
Specification value
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Sequence number 1)
Data delay time
(from address valid open
RD to data out
Read command recovery time
WR!Address before
Setup time
CS setup time before WR
Address hold time after WRT
WR pulse width
Data setup time before WR
Data hold time after WRI
Write command recovery time
Clock cycle
Clock high level pulse width
Clock low level pulse width
Clock rise time
Clock fall time
Gate high level pulse width
Gate low level pulse width
Gate setup time (to
CPf after gate hold time
Output delay time
(starting from CP+)
Output delay time
(from GATE+ to GATE+)||tt t||farAv-DV)
LRH-DZ)
treeTRH)
tsurAV-WL)
su(CSL-WL)|| tt||(WH-A)
(wrwL)
tsu(DV-WH)
th(WH-DV)
TreerWH
f wrcH)
W(GATEH)
AWIGATELL
Isu(GATEH-CH)
Tau(GATEL-CH)| |tt||f(CH-GATEL)
t(CH-GATEH)
fa(CL-Uv)
d(GATEL-OV)
SJ 20073—92
Continued Table 1
Condition 2)
VoH-2.0 V
Note: 1) The serial numbers of the parameters in this table are consistent with the serial numbers of the parameters in the timing diagram; 2) If there are no other provisions, Kuv=5±0.5 V, I=-55～125\C, Yss=0 VSpecification
Test requirements
Intermediate (before aging) electrical test (method
Final electrical test 1
(Method 5004)
Group A test requirements 2)
(Method 5005)
Group B V2Ae Test
Group C endpoint electrical test
(Method 5005)
Group C test added group
Group D landing point electrical test
(Method 5005)
SJ20073—92
Table 2 FE test requirements
points, New (see Ge 3)
B-level devices
A1, A2, A3, A7: A8, A9, A10,All
A1，A7
BI-level devices
A1, A2, A3, A7,A9
A1, A2, A3, A4, A7. A8. A9,
, Al. A2, A3, A4, A7. A0
A10,Al1
Exempt from Clause 4.5.3 of this Code
A2,A3,A8
Not required
A2, A8 (125 °C only)
Note: 1) PDA calculation is required for A1 and A7 (see Clause 4.2 of this Code). 2) Group A4 ((, G) is only used for identification (see 4.4.1 of this specification). Table 3 Group A electrical test
fot =2.U mA
foH =-400 μA
V=Vpn to 0V
Yo = Vop to 0.45 V
Except 7,=125°℃, the parameters, conditions, and specifications are grouped in A1. Except Tr--55C, the parameters, conditions, and specifications are grouped in A1. 8
Jcp=1 MHz, Vr-0 V
See 4.5.3 of this specification
A2A8 (only 125cC)
A10, A11
A2. A8 (only 125 °C)
Freight value
Vpr=0V, not tested with Vss
According to 6.2, T-=-25°℃, kinetic energy test is carried out at VpD=5.5V and VDD-4.5V respectively. Except T=-55°℃ and 125°C, they are grouped with A7. 10
FgAV-KLL
tsu(CSL-RL.)
ThRH-AV)
fdiRL-UV)
Vomr=2.0 V
Vot=0.8 V
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trAV-D
a(RH-D2)
LreerRH
(surA-WL)|| tt||seiCSL-W
thOWH-A)
fsuDV-WH)
freerWH
FW(GATEH)||tt| |W(GATEL)
IsuGATEH-CH)
a(GATEL-CH)
h(CH-GATEL)
ThCK-GATEH)
arcl-ov)
fa(GATEL-OV)
SJ20073-92
Continued Table 3
VoL=0.8 V
Except Tc-125C, the parameters, conditions and specification values ​​are the same as those grouped in A9. Except Tc--55 °C, parameters, conditions and specification values ​​are the same as those of A9 group specification values
SJ 20073-92
Note: @RI is suitable current limiting resistor, R2-1.5k@, CI-100 pF+20%:
③VzAP=400 V, t① pulse conversion time (tr1H) ≤50πs (10%～90%) measured at the device input. Figure 3 High voltage (YzAr) test circuit
Connect the device under test
TYKAOIKAca-
SJ20073—92
Aging start position:
Aging and life test circuit diagram
Test shop
Figure 5 AC test input/output waveform
C=150pF1)
Figure 6 AC test load circuit
Note: 1) CL includes the fixture capacitance.
Data bus
RD, WR
4 Quality assurance regulations
4.1 Sampling and inspection
SJ 20073-92
Figure 8 Read cycle timing diagram
Figure 9 Recovery timing diagram
Figure 10 AND gate timing diagram
Other regulations, sampling inspection procedures should be in accordance with GJB597 and GJB548 method 5005 regulations 4.2 Screening
Before identification and quality consistency inspection, all devices should be screened according to GJB548 method 5004 and Table 5 regulations.
TTKAONKAa-Yss=0 VSpecification
Test requirements
Intermediate (before aging) electrical test (Method
Final electrical test 1
(Method 5004)
Group A test requirements 2)
(Method 5005)
Group B V2Ae test
Group C endpoint electrical test
(Method 5005)
Group C inspection added group
Group D landing point electrical test
(Method 5005)
SJ20073—92
Table 2 FE test requirements
points, New (see Ge 3)
Class B devices
A1, A2, A3, A7: A8, A9, A10,All
A1，A7
B1 level devices
A1, A2,A3, A7,A9
A1, A2, A3, A4, A7. A8. A9,
, Al. A2, A3, A4, A7. A0
A10,Al1
Exempt from 4.5.3 of this specification
A2,A3,A8
Not required
A2, A8 (125 °C only)
Note: 1) PDA calculation is required for A1 and A7 (see 4.2 of this specification). 2) Group A4 ((, G) is only used for identification (see 4.4.1 of this specification). Table 3 Group A electrical test
fot =2.U mA
foH =-400 μA
V=Vpn to 0V
Yo = Vop to 0.45 V
Except 7,=125°℃, the parameters, conditions, and specifications are grouped in A1. Except Tr--55C, the parameters, conditions, and specifications are grouped in A1. 8
Jcp=1 MHz, Vr-0 V
See 4.5.3 of this specification
A2A8 (only 125cC)
A10, A11
A2. A8 (only 125 °C)
Freight value
Vpr=0V, not tested with Vss
According to 6.2, T-=-25°℃, kinetic energy test is carried out at VpD=5.5V and VDD-4.5V respectively. Except T=-55°℃ and 125°C, they are grouped with A7. 10
FgAV-KLL
tsu(CSL-RL.)
ThRH-AV)
fdiRL-UV)
Vomr=2.0 V
Vot=0.8 V
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trAV-D
a(RH-D2)
LreerRH
(surA-WL)|| tt||seiCSL-W
thOWH-A)
fsuDV-WH)
freerWH
FW(GATEH)||tt| |W(GATEL)
IsuGATEH-CH)
a(GATEL-CH)
h(CH-GATEL)
ThCK-GATEH)
arcl-ov)
fa(GATEL-OV)
SJ20073-92
Continued Table 3
VoL=0.8 V
Except Tc-125C, the parameters, conditions and specification values ​​are the same as those grouped in A9. Except Tc--55 °C, parameters, conditions and specification values ​​are the same as those of A9 group specification values
SJ 20073-92
Note: @RI is suitable current limiting resistor, R2-1.5k@, CI-100 pF+20%:
③VzAP=400 V, t① pulse conversion time (tr1H) ≤50πs (10%～90%) measured at the device input. Figure 3 High voltage (YzAr) test circuitbZxz.net
Connect the device under test
TYKAOIKAca-
SJ20073—92
Aging start position:
Aging and life test circuit diagram
Test shop
Figure 5 AC test input/output waveform
C=150pF1)
Figure 6 AC test load circuit
Note: 1) CL includes the fixture capacitance.
Data bus
RD, WR
4 Quality assurance regulations
4.1 Sampling and inspection
SJ 20073-92
Figure 8 Read cycle timing diagram
Figure 9 Recovery timing diagram
Figure 10 AND gate timing diagram
Other regulations, sampling inspection procedures should be in accordance with GJB597 and GJB548 method 5005 regulations 4.2 Screening
Before identification and quality consistency inspection, all devices should be screened according to GJB548 method 5004 and Table 5 regulations.
TTKAONKAa-Yss=0 VSpecification
Test requirements
Intermediate (before aging) electrical test (Method
Final electrical test 1
(Method 5004)
Group A test requirements 2)
(Method 5005)
Group B V2Ae test
Group C endpoint electrical test
(Method 5005)
Group C inspection added group
Group D landing point electrical test
(Method 5005)
SJ20073—92
Table 2 FE test requirements
points, New (see Ge 3)
Class B devices
A1, A2, A3, A7: A8, A9, A10,All
A1，A7
B1 level devices
A1, A2,A3, A7,A9
A1, A2, A3, A4, A7. A8. A9,
, Al. A2, A3, A4, A7. A0
A10,Al1
Exempt from 4.5.3 of this specification
A2,A3,A8
Not required
A2, A8 (125 °C only)
Note: 1) PDA calculation is required for A1 and A7 (see 4.2 of this specification). 2) Group A4 ((, G) is only used for identification (see 4.4.1 of this specification). Table 3 Group A electrical test
fot =2.U mA
foH =-400 μA
V=Vpn to 0V
Yo = Vop to 0.45 V
Except 7,=125°℃, the parameters, conditions, and specifications are grouped in A1. Except Tr--55C, the parameters, conditions, and specifications are grouped in A1. 8
Jcp=1 MHz, Vr-0 V
See 4.5.3 of this specification
A2A8 (only 125cC)
A10, A11
A2. A8 (only 125 °C)
Freight value
Vpr=0V, not tested with Vss
According to 6.2, T-=-25°℃, kinetic energy test is carried out at VpD=5.5V and VDD-4.5V respectively. Except T=-55°℃ and 125°C, they are grouped with A7. 10
FgAV-KLL
tsu(CSL-RL.)
ThRH-AV)
fdiRL-UV)
Vomr=2.0 V
Vot=0.8 V
TTKAONKAa-
trAV-D
a(RH-D2)
LreerRH
(surA-WL)|| tt||seiCSL-W
thOWH-A)
fsuDV-WH)
freerWH
FW(GATEH)||tt| |W(GATEL)
IsuGATEH-CH)
a(GATEL-CH)
h(CH-GATEL)
ThCK-GATEH)
arcl-ov)
fa(GATEL-OV)
SJ20073-92
Continued Table 3
VoL=0.8 V
Except Tc-125C, the parameters, conditions and specification values ​​are the same as those grouped in A9. Except Tc--55 °C, parameters, conditions and specification values ​​are the same as those of A9 group specification values
SJ 20073-92
Note: @RI is suitable current limiting resistor, R2-1.5k@, CI-100 pF+20%:
③VzAP=400 V, t① pulse conversion time (tr1H) ≤50πs (10%～90%) measured at the device input. Figure 3 High voltage (YzAr) test circuit
Connect the device under test
TYKAOIKAca-
SJ20073—92
Aging start position:
Aging and life test circuit diagram
Test shop
Figure 5 AC test input/output waveform
C=150pF1)
Figure 6 AC test load circuit
Note: 1) CL includes the fixture capacitance.
Data bus
RD, WR
4 Quality assurance regulations
4.1 Sampling and inspection
SJ 20073-92
Figure 8 Read cycle timing diagram
Figure 9 Recovery timing diagram
Figure 10 AND gate timing diagram
Other regulations, sampling inspection procedures should be in accordance with GJB597 and GJB548 method 5005 regulations 4.2 Screening
Before identification and quality consistency inspection, all devices should be screened according to GJB548 method 5004 and Table 5 regulations.
TTKAONKAa-8 V
Except Tc-125C, the parameters, conditions and specification values ​​are the same as those of group A9. Except Tc--55 °C, the parameters, conditions and specification values ​​are the same as those of group A9
SJ 20073—92
Note: @RI is a suitable current limiting resistor, R2-1.5k@, CI-100 pF+20%:
③VzAP=400 V, t① pulse conversion time (tr1H) ≤50πs (10%～90%) measured at the device input. Figure 3 High voltage (YzAr) test circuit
Connect the device under test
TYKAOIKAca-
SJ20073—92
Aging start position:
Aging and life test circuit diagram
Test shop
Figure 5 AC test input/output waveform
C=150pF1)
Figure 6 AC test load circuit
Note: 1) CL includes the fixture capacitance.
Data bus
RD, WR
4 Quality assurance regulations
4.1 Sampling and inspection
SJ 20073-92
Figure 8 Read cycle timing diagram
Figure 9 Recovery timing diagram
Figure 10 AND gate timing diagram
Other regulations, sampling inspection procedures should be in accordance with GJB597 and GJB548 method 5005 regulations 4.2 Screening
Before identification and quality consistency inspection, all devices should be screened according to GJB548 method 5004 and Table 5 regulations.
TTKAONKAa-8 V
Except Tc-125C, the parameters, conditions and specification values ​​are the same as those of group A9. Except Tc--55 °C, the parameters, conditions and specification values ​​are the same as those of group A9
SJ 20073—92
Note: @RI is a suitable current limiting resistor, R2-1.5k@, CI-100 pF+20%:
③VzAP=400 V, t① pulse conversion time (tr1H) ≤50πs (10%～90%) measured at the device input. Figure 3 High voltage (YzAr) test circuit
Connect the device under test
TYKAOIKAca-
SJ20073—92
Aging start position:
Aging and life test circuit diagram
Test shop
Figure 5 AC test input/output waveform
C=150pF1)
Figure 6 AC test load circuit
Note: 1) CL includes the fixture capacitance.
Data bus
RD, WR
4 Quality assurance regulations
4.1 Sampling and inspection
SJ 20073-92
Figure 8 Read cycle timing diagram
Figure 9 Recovery timing diagram
Figure 10 AND gate timing diagram
Other regulations, sampling inspection procedures should be in accordance with GJB597 and GJB548 method 5005 regulations 4.2 Screening
Before identification and quality consistency inspection, all devices should be screened according to GJB548 method 5004 and Table 5 regulations.
TTKAONKAa-
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