SJ 20160-1992 Semiconductor integrated circuits JT54S194 and JT54S195 S-TTL shift registers detail specification

time: 2024-08-05 12:51:31
  • SJ 20160-1992
  • in force

Basic Information

standard classification number

  • China Standard Classification Number:

    >>>>L5962

associated standards

Publication information

Other Information

Introduction to standardsDescription (Translated English) / download

Skip to download

Summary:

SJ 20160-1992 Semiconductor Integrated Circuits JT54S194 and JT54S195 Type S-TTL Shift Register Detailed Specification SJ20160-1992 Standard Download Decompression Password: www.bzxz.net
Standard contentStandard content

Some standard content:

Detail specification for types JT54S194 and JT54S195SHIFT RFGISTERS of S-TTL semiconductor integrated circuits circuits1992-11-19 Issued
1993-05-01 Implemented
The Ministry of Machinery and Electronics Industry of the People's Republic of China 1 Scope
1.1 Subject matter
1.2 Scope of application
1.3 Classification
2 Reference documents
3 Requirements
3.1 Detailed requirements
3.2 Design, structure and dimensions
3.3 Lead materials and coating
3.4 ​​Electrical characteristics
3.5 Electrical test requirements
3.6 Marking
3.7 Division of microcircuit groups
4 Quality assurance regulations|| tt||4.1 Sampling inspection
4.2 Screening
4.3 Authentication inspection
4.4 Quality consistency inspection
4.5 Inspection method
5 Delivery preparation
5.1 Packaging requirements
6 Notes
6.1 Intended use
6.2 Ordering information
6.3 Abbreviations, symbols and definitions
Substitution
People's Republic of China Electronic Industry Military Standard Semiconductor Integrated Circuits
JT54S194 and JT54S195 Types
S-TTL Shift Register Detailed Specification
Detaif specification for types JT54S194 and JT54S195SHIFT RFGISTERS of S-TTL semiconductor integrated circuits1 Scope
1.1 Subject content
SJ 20160-92
This specification specifies the detailed requirements for semiconductor integrated circuits JT54S194 and JT54S195 type S-TTL shift registers (hereinafter referred to as devices).
1.2 Scope of application
This specification applies to the development, production and procurement of devices. 1.3 Classification
The devices given in this specification are classified according to device model, device grade, packaging form, rated value and recommended operating conditions. 1.3.1 Device number
The device number should be in accordance with the provisions of Article 3.6.2 of GJB597 "General Specification for Microcircuits". 1.3.1.1 Device model
The device models are as follows:
Device model
JT54S194
FT545195
1.3.1.2 Device grade
Device name
4-bit parallel shift register (parallel access) 4-bit shift register (parallel access, JK input) The device grade should be Class B as specified in Article 3.4 of GJB597 and Class B as specified in this specification. 1.3.1.3 Packaging Type
The packaging type is as follows:
Approved by the Ministry of Machinery and Electronics Industry of the People's Republic of China on November 19, 1992 and implemented on May 1, 1993
1.3.2 Absolute Maximum Ratings
The absolute maximum ratings are as follows:
Power Supply Voltage
Input Current
Storage Voltage
Power Consumption"
Lead Soldering Temperature Resistance (10 s)
Junction temperature 2)
Package type (GB7092 "Outline Dimensions of Semiconductor Integrated Circuits") D16S3 (ceramic dual-inline package)
F16X2 (ceramic flat package)
HI6X2 (ceramic sealed flat package)
J16S3 (ceramic sealed effective-inline package)
Note: 1) The device should be able to withstand the increased power consumption when the test input short-circuit current (Is) is applied. 2) Except for the aging test in Article 4.3 of this specification, the junction temperature should not exceed 175°C. 3.3 Recommended operating conditions
The recommended operating conditions are as follows:
Power supply voltage
Input high-level voltage
Input low-level voltage
Output high-level current
Output low-level current
Working environment amplitude
Pulse amplitude
Ma,M, JT54S194
D input
Setup time
Hold time
SH/LD JT54S195
CR invalid state
2 Referenced documents
GB3431.1—82 Semiconductor integrated circuit symbol electrical parameter symbol GB3431.2—86 Semiconductor integrated circuit symbol terminal function symbol maximum
-1 000
GB 3439—82 Basic principles of semiconductor integrated circuit TTL circuit test methods GB4590—84 Mechanical and climatic test methods for semiconductor integrated circuits GB4728.12-851 Graphical symbols for L-type diagrams Binary logic units GB7092 Dimensions of conductor integrated circuits
GJB548--88 Test methods and procedures for microelectronic devices GJB597—88 General specifications for microcircuits
GJB/Z105 Manual for control of electrostatic discharge of electronic products
3 Requirements
3.1 Detailed requirementsWww.bzxZ.net
All requirements shall comply with the provisions of GJB597 and this specification. 3.2 Design, structure and dimensions
The design, structure and dimensions shall comply with the provisions of GJB597 and this specification. 3.2.1 Logic symbols, logic diagrams and lead-out terminal arrangement Logic symbols, logic diagrams and lead-out terminal arrangement shall comply with the provisions of Figure 1. The lead-out terminals are arranged as a top view, a.JT54S194
Logic symbol
External lead array
Logic diagram
.JT54S195
Logic symbol
1nCR—国
1 5 JD2
M1[SHIFT]
M2LOAD】
>C3/1-
ait 14 t
+-02t 13 1
Q3t12J
External lead array
Logic diagram
19 H/LD
-oot 15
GLE 141
--02( 13
23f 11 ?
(7)D3
Figure 1 Logic symbol, logic diagram and pin arrangement 3.2.2 Function table and timing diagram
The function table and timing diagram are as follows:
a.JT54S194
Function table
Timing diagram
!Left shift prohibited
b.IT54S195
Function table
Timing diagram
Shift-
Note: H is high level: fire low electrical half: low to high electrical half jump, X is any state: ds, dd, d, DD,, DD, the steady-state input level of the terminal: QQInQ2, Q is specified The levels of Qo, Q1, Q2, Q2 before the steady-state input condition is established; Qm, QQn, Qn are the levels of QQ, Q2, Q2 before the clock is closest to t: d3 is the complement of d1: Q3o is the complement of Qc; Qc, 0 are the complement of Qom, Qm, 3.2.3 Electrical schematics
The manufacturer shall submit the electrical schematics to the appraisal agency before appraisal, and the electrical schematics shall be filed by the appraisal agency for future reference. 3.2.4 Package form
The package form shall comply with the provisions of Article 1.3.1.3 of this specification. 3.3 Lead materials and coating
Lead materials and coating shall comply with the provisions of Article 3.5.6 of GJB597. 3.4 Electrical Characteristics
The electrical characteristics shall comply with the requirements of Table 1 of this specification
Output high level voltage
Output low level voltage
Input clamping voltage
Input at maximum input voltage
Input high level current
Input low level current
Input short-circuit current 23
Power supply current
Maximum clock frequency
Transmission delay time
Table 1—1Electrical characteristics of JT54S194
Condition 1
(If not otherwise specified, -55℃≤T≤125℃) Vcc=4.5 V, V-2.0 V, lon--1 000 μVcc=4.5 V, Vm*2.0 V, Vu-0.8 V, JuL-20 mAVuc=4.5 V, Ix=-18 mA
Vce-5.5 V, V-5.5 V
Ve-5.5 V, V-2.7V
Vx=-5.5 V, V-0.5 V
Vcc=5.0 V,
R,=280 0,
G=15 pF
Note: 1) The complete test conditions are listed in Table 3. 2) Only one output terminal can be short-circuited at a time.
CR is a fixed voltage.
CP→year
Specification value
Output high level voltage
Output low level voltage
Input clamp voltage
Input current
Input low level current
Input short-circuit current22
Power supply current
Maximum clock frequency
Propagation delay time
Table 1—2 Electrical characteristics of JT54S195
Conditions》
(Unless otherwise specified, -55C≤T≤125C) Vcc=4.5 V, Vm-2.0 V, 1 000 μVc=4.5 V, Ym-2.0 V. V=0.8 V.ful-20 mAVe-4.5 V, Ik=-=18 mA
Ver=5.5 V, V-5.5 V
Vec=5.5 V, V-2.7V
Ve~5.5 V, Y-0.5 V
Vce=5.5 V
Vcr=-5.0 V,
R,-280 Q,
G-15 pF
Note:) The complete test conditions are listed in Table 3. 2) Only one output terminal can be short-circuited at a time. 3.5 Electrical Test Requirements
CR-Any Q
CP→Any—α
Specification Values
The electrical test requirements for each level of the device shall be the relevant sub-divisions specified in Table 2 of this specification, and the electrical tests for each sub-division shall be in accordance with the provisions of Table 3 of this specification.
Tip: This standard content only shows part of the intercepted content of the complete standard. If you need the complete standard, please go to the top to download the complete standard document for free.
Please remember: "bzxz.net" is the combination of the first letters of the Chinese pinyin of the four Chinese characters "standard download" and the international top-level domain name ".net". ©2024 Standard download websitewww.bzxz.net Mail:[email protected]