GB/T 5693-1985 Specification for CAMAC multi-chassis system structure branch information highway and A1 type CAMAC chassis controller

This standard is applicable to nuclear instruments and can also be used in other occasions where modular electronic instruments and equipment are required for signal input and output transmission to complete digital data processing. Such instruments and equipment are generally used in conjunction with control devices, computers or other automatic data processors. GB/T 5693-1985 CAMAC multi-chassis system structure branch information highway and A1 type CAMAC chassis controller specification GB/T5693-1985 Standard download decompression password: www.bzxz.net

1 Introduction
1.1 Overview
National Standard of the People's Republic of China
CAMAC organization of multi -crate systems specification of the branch -bighwayandCAMAC cratecontrollertypeA1UDC 621.039-791
2 : 621.317.39
GB 5693—85
IEC552-1977
This standard is equivalent to the international standard IEC552(1977) (Specification of branch -bighway and CAMAC cratecontrollertypeA1 of CAMAC multi -crate system structure).
This standard makes the following editorial changes to IEC552: a. IEC The content of Article 1.1 of IEC552 is not included in this standard*. b. This standard has a sub-chapter. The arrangement format of the articles, clauses and items shall be written in accordance with GB1.1-1 "General provisions for the preparation of standards for standardization work guidelines".
e. The original text of IEC552 uses boldface to indicate the articles that must be followed. This standard uses a thin solid line under the article to indicate the articles. 1.2 China's
GB5591-85** "Modular instrument system for data processing, CAMAC system" stipulates a system that can make sensors and The basic characteristics of the CAMAC modular instrument system for interfacing other equipment with digital control equipment and computers. The CAMAC chassis data highway is the basis for mutual communication between the modules and controllers of a chassis system. Multiple chassis systems can form one or more larger structural units, called branches. In a branch, the chassis controllers in several (up to 7) chassis are interconnected to a branch driver by a branch information highway.
This standard specifies the transmission from the chassis controller and the branch driver through the CAMAC chassis data highway. The standard 132-way connector is connected to the signal, timing and logic structure of the branch information highway.
Appendix A specifies the characteristics of the chassis controller that affect the interchangeability of hardware and software. This appendix can be used as a formal specification for the standard A1 type CAMAC chassis controller (as a supplement to this standard) or as a general recommendation with the purpose of maintaining uniformity between chassis controllers.
1.3 Scope
This standard is applicable to nuclear instruments and can also be used in other occasions where modular electronic instruments and equipment are required for signal input and output transmission to complete digital data processing. Such instruments and equipment are generally used in combination with control devices, computers or other automatic data processors. For nuclear instruments and control systems, other structural forms of multi-chassis systems can also be used. In detail
a: This standard is applicable to a system consisting of several CAMAC chassis or CAMAC combined chassis (each chassis has a controller * The original content should state IEC552 and other standards and EURATOM rights and interests. When adopting it, it is not necessary to write the national standard of my country. ** Originally named "[EC516]" in IEC 552, it has now been adopted as our national standard. Later, the Chinese e
can be used as a sharp
100e-1n01 implementation
GB 5693-85
and some modules) are connected to each other by a bit parallel branch information highway. b. This standard applies to the word serial transmission between up to seven chassis and one branch driver. This word string transmission contains no more than 24 characters as a parallel transmission of a word. c. This standard does not involve the internal structure of the chassis controller and branch driver and the physical characteristics of the branch information highway itself. It only stipulates those aspects related to the compatibility between the various parts of the system and the compatibility with the A1 type chassis controller. Any equipment or system that can be called compliant with the CAMAC branch information highway specification must comply with all the mandatory regulations in this standard (except Appendix A). Any equipment made into a CAMAC plug-in must also comply with the mandatory regulations in GB569185. Any equipment that can be called as complying with the A1 type CAMAC chassis controller specification must comply with all the mandatory provisions in Appendix A of this standard.
Equipment connected to the branch information highway does not have to fully comply with this standard, nor does it have to be made into CAMAC components, but it must at least be compatible with the full operation of all the features of the branch information highway and chassis controller specified in this standard without interfering with them. 2 Explanation of this standard
This standard is a continuation of GB5691-85 and should be read in conjunction with GB5691-85. This standard does not replace or modify GB5691-85.
All the provisions that require compliance are indicated by a thin solid line below them*. The word "must" is often used in these provisions. The word "should" indicates a preferred method that should be followed unless there are sufficient reasons to oppose it. The word "may" indicates a good method that is allowed to be selected. The word "reserved" means that it cannot be used before detailed regulations are made. The word "free" means that a special use is allowed within the scope of the standard without restriction. 3 Branches
The multi-chassis CAMAC system consists of one or several branches, each branch having a branch information highway. The branch information highway is the link for interconnecting the branch driver with several chassis controllers. During each branch operation, the branch driver can communicate with up to 7 chassis controllers.
All branch drivers and chassis controllers have standard branch information highway ports**, through which they can be connected to the branch information highway. Each port consists of a 132-way connector with specified contact positions and signal conventions (for connecting 65 signal lines and their respective routes and cable shielding). Each chassis controller has two ports that are identical and connected internally to enable the branches to form a chain structure as shown in Figure 1. Other structures are also possible, as shown in Figure 2, where the branch driver is not at the end of the branch and several chassis are connected with only one port. * In FCs62, it is a black letter book.
** refers to the network terminal and the like
CB 569385
Seven-foot machine chapter one
Seven boxes
Terminal unit
Branch information highway
Cabinet controller
Branch information highway
Chassis controller
Distribution information highway
Branch actuator and terminal
Figure 1 Chain structure CAMAC branch
Seven boxes one
Seven boxes one
Seven machines new
GB5693—85
Chassis light controller
Chassis controller
Chassis controller
Termination unit
Figure 2 Another structural form of CAMAC branch branch information highway
Branch driver (without terminal)
Branch information station
WWm.GB5693—85
In addition to the usual "online" state, the chassis controller also has an "offline" state, in which it only maintains a mechanical connection with the branch and does not participate in (or interfere with) all branch operations. If necessary, the branch driver can identify which are the chassis addresses of the online chassis controller.
The basic mode of branch operation is the "command" mode. The branch driver is usually connected to the system control device or computer. During each branch operation, the branch driver issues a command, which includes chassis address information for selecting one or more chassis controllers. Each chassis controller being sought receives commands from the branch information highway and generates corresponding chassis data step commands (station number, sub-address and function). During the "read" operation, the module generates data signals and adds them to the chassis data road read line, and then the chassis controller transmits them to the data line of the branch information highway and receives them by the branch driver. During the "write" operation, the branch driver generates data signals and sends them to the branch information highway, and the chassis controller transmits them to the chassis data path write line, and then receives them by the module. During other command operations, there is no read or write data transmission through the branch information highway. In the branch, there are two "request processing" modes for the branch driver to respond to the request attention signal issued by the module. One is single-level request processing, in which the chassis controller combines the request attention signals in the chassis into a common "branch request" signal and sends it to the branch. This method only indicates that a request has occurred, but does not identify them in detail. The other is multi-level request processing, using the "hierarchical L mode" branch operation, the branch driver can identify 24 different requests. The branch driver issues a hierarchical L query (usually after receiving the branch request signal), and each online chassis controller responds with a 24-bit hierarchical L word formed by selecting and rearranging the request attention signals in the chassis. The hierarchical L words from each chassis are merged on the branch information highway and sent to the branch driver. In the branch information highway port, the data line is used to transmit information in either direction between the chassis controller and the branch driver when operating in command mode, and is also used to carry the "request pattern" (hierarchical L word) in hierarchical L mode operation. Any mode of transmission through the branch information highway port is controlled by interlocking timing signals, which automatically adjust the timing of each branch operation to adapt to the actual transmission delay and the specific performance of the controller. The initialization signal is the only "common control" signal transmitted to the peach box data path through the branch information highway port. Use of each line of the branch information highway port Each line of the branch information highway port must be used in accordance with the requirements that must be followed as detailed in the following clauses. Table 1 lists the names, standard symbols and sources of generation of the signals. To distinguish them from the corresponding lines in the chassis data path, each line on the branch information highway port is prefixed with B. For example, the F line carries the function code in the chassis data path, while the BF line is carried on the branch information highway port. Table 1 Signal line name at the branch information highway port
Chassis address
Sub-address
Read and write
Command acceptance
BCR1BCR7bzxZ.net
DN.1,2.4,8.16
BA1.2.4.8
BF1,2,4.8,16
BRW1-BRW24
Source
Branch driver
Branch driver
Branch driver
Branch driver
Branch driver (W)
or chassis controller
(R, GL)
Chassis controller
Chassis controller
Number of signal lines
Each line addresses a chassis in the branch
Division station number
A line of the same chassis data path
F line of the same chassis data path
Used for writing data, reading data and classification
Q line of the same chassis data path|| tt||X line of the same chassis data path
Request processing
Common control
Branch request
Grading L inquiry
BTB1-BTB7
BV6~BV?
BV1~BV5
GB569385
Continued table 1
Source
Branch driver
Chassis controller
Chassis controller
Branch driver
Branch driver
Number of lines
Indicates that there is a command, etc.
Each line represents a chassis controller
Data, etc. exist
Indicates that there is a request
Grading L operation
Same as the chassis data line 2 lines
For future use
For users to use for non-standard needs
Note: Each signal line has a separate national line, and there are two lines for the shield connection of the branch information highway cable (if the cable has a shield). 4.1 Command
The command signal is used in command mode operation. At this time, the signal on the BG line (see 4.4.2) must be in the "0" state. The command signals are sent by the branch driver to the BCR, BN, BA and BF lines of the branch information highway port, which are described as follows: 4.1.1 Chassis Address (BCR1-BCR7)
The seven chassis controllers that can be addressed in any branch operation must each be associated with a different BCR line (although all branch highway ports are equipped with seven BCR lines. Therefore, each chassis controller must have a means for selecting the corresponding BCR line (called BCR;), such as a switch or a temporary connection line. The serial numbers of the BCR lines assigned to each chassis do not necessarily have to match the actual arrangement order of the chassis in the branch. In order to select several chassis in the same operation, the branch driver can generate signals on several BCR lines at the same time. It is recommended that the chassis controller should be provided with means to prevent interference from parasitic signals on the selected BCR line. For example, the BCR signal sent by the branch information highway or the internal signal caused by it can be adjusted by the integration method. It can be seen in Section 4.3 that each-chassis controller not only Associated with one BCR line, and also associated with one of the seven BTB lines.
If more than one online chassis controller is connected to the same BCR line, the branch is in an ineffective state. A method to reduce this risk is proposed in Section 5.4. 4.1.2 Station number (BN1, 2-4.8, 16)
The signals on these five lines represent the binary-coded station numbers used in the selected one or more chassis, which are decoded in the chassis controller.
In the chassis controller, the allocation of these 32 codes is shown in Table 2. The chassis controller occupies at least one ordinary station, and the remaining ordinary stations are each individually addressed with a corresponding station number. In addition: there are station numbers for multiplexing all ordinary stations or those stations indicated by the contents of the station number register (SNR) and station numbers that can be used to address the controller and its extensions (regardless of their location in the chassis). N code
N(1)- (23)
N (25, 27. 29, 31)
GB5693-85
Table 2 Station numbers for chassis controllers
Addressing the corresponding ordinary station
Only pre-selected ordinary station
Addressing all ordinary stations
Addressing only chassis controllers
Addressing only chassis controllers
4.1.3 At address (BA12, 48, 16)
B, S1, S2
The ordinary station occupied by the controller does not need to be addressed. Operation without chassis data path
During command mode operation, the addressed online chassis controller must forward the signals on these five lines to the function lines (F 1, 2, 4, 8, 16) of the chassis data path.
4.1.4 Function (BF1, 2, 4, 8, 16) During command mode operation, the addressed online chassis controller must forward the signals on these five lines to the function lines (F1, 2, 4 to 8, 16) of the chassis data path.
4.2 Data and Status
4.2.Read and Write (BRW1 to BRW24)
In command mode read operations, these 24 lines are used to transfer data from each addressed chassis controller to the branch driver, with BRW1 corresponding to chassis data path R1, etc. In command mode horse operations, they are used to transfer data from the branch driver to each chassis controller, with BRW1 corresponding to chassis data path W1, etc. In hierarchical L mode operations, they are used to transfer the request pattern of each online chassis controller in the branch to the branch driver. In command mode write operations, only the branch driver can generate a "1" state input on these lines. In hierarchical 1 mode operations and command mode read operations, only the addressed online chassis controller can generate a "1" state output on these lines. 4.2.2 Response (BQ)
In a command mode operation with chassis data path operation, each addressed online chassis controller must generate a BQ signal (BQ=Q) corresponding to chassis data path Q. In a command mode operation to test a certain characteristic state of the chassis controller without chassis data path operation, the chassis controller must issue a corresponding BQ response. At other times, the chassis controller must generate BQ=0. The signal on the branch driver BQ line is the "OR" combination of the BQ signals from all chassis controllers. 4.2.3 Command Acceptance (BX)
In a command mode operation with chassis data path operation, each addressed online chassis controller must generate a BX signal (B=X) corresponding to the lower chassis data path X. ). In all other command operations, if the chassis controller can accept this command, BX=1 must be generated, if it cannot accept this command, BX=0. The signal on the BX line of the branch driver is an "OR" combination of the BX signals from all chassis controllers. 4.2.3.1 Command Acceptance (X and BX) Disable In a chassis controller or branch driver that can monitor X or BX responses and initiate a system alarm when X or BX=0, GB5693-85
should also be provided with a "command acceptance disable" operation mode that does not cause an automatic system alarm when X or BX=0. This operation mode will allow systems that may contain early plug-ins to work normally. Because some early plug-ins do not have the function of generating and sending X and BX signals, X=0 is always used. When completing a block transfer operation in address scan mode, the combination of Q=0 and X=0 should not cause an automatic system alarm.
4.2.3.2 Command Acceptance (BX) Response to Hierarchical L Query (BG) The BX response generated by CCA1 during command mode operation is specified in detail (see Section 4.2.3 and Chapter A.8). Since hierarchical L operations are usually multi-way addressed, in this case, the BX signal on the branch driver does not actually indicate that all chassis have responded to this operation. Therefore, the BX response to BG is not specified, but Recommendation 8 states that when CCA1 is addressed in a hierarchical L operation, it should generate BX=0. b. During hierarchical L operation, the branch driver should not respond to the BX status. 4.3 Timing (BT A.BTB1～BTB7)
The timing of all command modes and hierarchical L branch operations is controlled by the branch timing signal. The branch driver uses the signal of the common BTA line to start the operation, and each addressed chassis controller responds with the signal on its own dedicated BTB line. Each branch information highway port has seven BTB lines, but each chassis controller only uses one BTB, line corresponding to the BCR line addressing the chassis.
Each online chassis controller must generate BTB;=1 when it is not addressed, so that the branch driver (and other chassis controllers) can distinguish which BTB lines 41 are online chassis (BTB=1) and which are offline chassis or vacant chassis (BTB,=0) (see Section 5.4).
The branch driver generates BTA1 to indicate that a command or hierarchical L query is appearing at its port, and maintains this signal until the driver receives the last BRW or BQ information. During branch operation, BTB,=0 is generated when the chassis controller has established data or BQ information.
The timing signal must be generated through the intrinsic OR gate output, and the signal transition time (the time for the signal to jump between 10% and 90% of the specified value) must be within 100±50ms. It is recommended that the chassis controller should be equipped with protection measures to prevent the BTA line from being interfered by dust signals. For example, the BTA signal sent from the branch information highway or the internal signal caused by it can be adjusted by the integral method. The complete timing relationship is described in Chapter 5. 4.4 Request processing
The request attention (L) signal sent from the plug-in of any part of the branch usually requires the generation of a corresponding command or command sequence. There are two ways of request processing for the branch, one is to use the separate request signal method, and the other is to use the hierarchical L inquiry signal method. 4.4.1 Branch Request (BD)
Each chassis controller can generate a request signal, which is a logic function of the L signal on the chassis data road, connected to the common branch request line (BD) L through an intrinsic OR gate. There is no limit on the time that the BD signal can change. The signal transition time (the time for the signal to jump between 10% and 90% of the specified value) must be within the range of 100±50ns. The delay between the time when the L signal on the control station of the chassis controller reaches a stable "1" state or "0" state and the time when the BD signal on the branch information road port of the same chassis controller reaches a corresponding stable "1" state or "0" state, and the delay between the time when the BD signal on the branch information road port of the same chassis controller reaches a corresponding stable "1" state or "0" state, shall not exceed 400nS. This maximum delay is due in part to the chassis controller and in part to some other unit that processes the L signal (e.g., the LAM classifier associated with the A1 chassis controller. The maximum delay caused by the A1 chassis controller is specified in Section A.9.2. 4.4.2 Classification L Request (BG)
The branch driver initiates classification L mode operation by generating a classification L request signal (BG) (accompanied by the BCR signal that addresses all connected chassis). Each addressed chassis controller generates a 24-bit classification 1. word code on the BRW line, and the branch driver reads the "OR" combination of these word codes. In each chassis, the chassis data path L signals are classified, and the selected related signals are assigned to the appropriate bits of the classification L word.
A word code read by the branch driver can indicate which chassis need attention, or which action is required (such as program interruption or automatic social, use the point princess station public engineering! Students are more excellent students arranged in the second room for the sake of uniformity, GB 5693-85
It is recommended that the priority arranged on the BRw(n+1) line should be higher than that on the BRw(n) line. The A1 type chassis controller provides an additional means of access request attention signal (see A.9.4 and Table 9) 4.5 Common control
4.5.1 Branch initialization (BZ)
The branch initialization signal (BZ) is generated by the branch driver. It has absolute priority over all other signals in the branch. The usual branch timing signal is not used with BZ. In order for the chassis controller to distinguish and prevent interference from short-term parasitic signals, the branch driver must keep BZ=1 for at least 10μs, and no graded L or command mode operation shall be generated during the subsequent 5μs. 4.5.2 Initialization (Z), clearing (C) and prohibition of chassis data path, (I) When the chassis controller receives a branch initialization signal (B2) that lasts for a period exceeding the minimum value (specified as 3±1us), it must start generating chassis as required in GB569185. The data path initialization signal (Z) and busy signal (B) are generated, and the selection signal (S2) is generated. Except for B and S2, which must be followed, whether S1 is generated or not is optional, and other units connected to the chassis data path cannot rely on its function.
All chassis controllers must have the means to generate chassis data path clear (C) and disable (I) signals. There are no branch information highway lines corresponding to the chassis data path common control signals C and I. The chassis controller should be able to generate chassis data path Z and C signals and generate and remove chassis data path I signals according to the command side operation specified in Table 9. The chassis controller can also generate chassis data path common control signals based on the signals of the front panel, unless specifically prohibited (as in the A1 type chassis controller
4.6 Reserved lines and free lines (BV1~BV7) All branch information highway ports are equipped with signal lines and return lines. If there is more than one port as in the chassis controller, the contacts of the corresponding lines on these ports must be jumpered. 4.6.1 Free lines (BV1~BV5)
There is no standard usage for these lines, but the use of these signal lines (BV1~BV5) and their return lines (BV1R~BV6R) must comply with the relevant provisions of 41 of this standard. The signals on the BV1~BV5 lines must comply with the provisions of Chapter 7 and cannot be used as other types of signal lines or power lines, etc. Any signal that is not synchronized with the branch operation should be provided by a signal source that meets the transition times specified in Articles 4.3 and 4.4.1. 4.6.2 Reserved lines (BV6~BV7)
These lines are reserved for future use, and their allocation will be specified in detail according to the proposed needs. 5 Branch operation
All information transfers (read data, write data, Q, X and classification L) through the branch information common port constitute a branch operation. The timing of each operation is controlled by the branch timing signals BTA and BTB1 to BTB7 and can be divided into four stages as specified in Tables 3 and 4 and FIG. 4.
GB 5693--.85
Table 3 Timing of command mode operation
Actions in branch driver
1. Create branch command (with
and write data)
2. Compensate signal offset
1. Wait for
BTB;-0
2. Compensate signal offset
3. Accept BQ and BX
(and read data)
1. Wait for
BTB;=1
2. Cancel command (and write
Start next The order of the operation, the change of the signal and the direction, the action of the machine error controller "1. Start the chassis data path operation 2. Establish BQ and BX (and read data on the branch information road or write data on the lead chassis data road) AOBTB: 1. Complete the chassis data path operation 2. Remove BQ and BX from the branch information road (and read data) during the whole operation and BG=0. When the command is required, the action shown in the brackets is executed. 5693— 85
Phase 1, the branch driver receives a branch command (including write data when writing command) or a classification query (BG) and the corresponding chassis address (BCR) at its end. After a delay of compensating for the total number of sign deviations, it generates BTA-1 and starts the next stage. Segment 2, each chassis controller addressed responds to A=1. When operating in command mode, the chassis controller starts the chassis data path operation and establishes Q, X and some read data at its port; when operating in classification mode, it establishes classification mode information at its port. Then it generates BTB:=0 on its BTB dedicated line. Only when the branch driver receives BTB=0 from all addressed chassis controllers, it starts the operation of a segment. Segment 3, the branch driver introduces a segment to compensate for the total number of sign deviations, and then receives Q, X and read data or classification mode information. It generates BTA=0 and starts the operation of the next stage.
In stage 4, each addressed chassis controller responds to BTA=0. In command mode operation, it ends the chassis data bus operation and removes the Q, WRITE and READ data at its port. In tiered operation, it removes the tiered WRITE information at its port. Then its BTB line is set to BTR:=1:
When the branch driver receives BTB=1 from all addressed chassis controllers, it ends stage 4. After that, it can start another branch operation (initiate a new command, write data or tiered query signal), or it can temporarily not operate (at this time, the original signal is removed). During the entire operation, the BTB line corresponding to the "talking" and vacant chassis controllers remains in the "0" state, and the BTL line corresponding to the unreachable connection remains in the "1" state. During the period of each stage, the timing sequence is automatically adjusted to adapt to the actual signal delay occurring on the branch information road and the response time required by the chassis controller.
The timing of command mode operation is described in Article 3.1 [Details are also available; the classification and operation standards are described in Article 5.2. In practice, the transmission delay of branch data is different. This signal offset problem is described in Article 5.3. If the branch driver or the addressed chassis controller cannot respond to the timing signal in the specified sequence, the branch operation cannot be completed. Therefore, the branch driver should be equipped with some form of time-limit device to monitor the situation where the operation cannot be completed within a specified time so that appropriate adjustments can be made. For the prevention of operation errors caused by addressing a vacant or offline chassis controller, the relevant methods described in Article 5.4 can be used.
The relationship between the branch information road operation and the chassis data road operation of the addressed chassis 5 must meet the requirements of Table 3 and GB5691--85.
The timing relationship between the chassis data selection communication (S1 and S2) and the branch timing signals (BTA and BTB) is specified in detail in the A1 chassis controller (see Section A.7). In the implementation of the chassis controller, this timing relationship will depend on whether there are registers for the command and data.
5.1 Command Mode Operations
The timing of command mode operations is shown in Table 3.
The following sections describe the various stages of a read operation and explain how other operations differ from a read operation. In any operation, one or more chassis may be interrupted. 5.1.1 Read Operation: Timing of Stage 1
(Function 7) Figure 3[.
B(CR.NAF)
(internal delay -
GB 5693-85
Branch operation
Earliest
Last earliest
Chassis data path operation
Figure 3 Branch read operation preparation
Next branch connection part
Action in bd
Verification delay
Action in cciFrom the branch information road
BQ and BX
(and read data)
During the whole operation, BG=0
When the command is required, the action shown in the brackets is executed
GB 5693-85
Stage 1, the branch driver sends a branch command (including write data when writing command) or a hierarchical query (BG) and the corresponding right box address (BCR) at its end. After compensating the delay of the sign deviation, it generates BTA-1 and starts the next stage. Section 2, each chassis controller that is addressed responds to A=1. When operating in command mode, the chassis controller starts the chassis data path operation and establishes Q, X and some read data at its port; when operating in hierarchical L mode, hierarchical L information is established at its port. Then BTB:=0 is generated on its BTB dedicated line. Only when the branch driver receives BTB=0 from all addressed chassis controllers, it starts a stage of operation. In stage 3, the branch driver enters a period of time to compensate for the number shift, and then receives Q, X and read data or level L information. It generates BTA=0 and starts the next stage of operation.
In stage 4, each addressed chassis controller responds to BTA=0. In command mode operation, it ends the chassis data transmission operation and removes Q, X and read data at its port. In level operation, it removes level L information at its port. Then its BTB dedicated line generates BTR:=1:
When the branch driver receives BTB=1 from all addressed chassis controllers, it ends stage 4. After that, it can start another branch operation (constructing a new command, writing data or level query signal), or it can temporarily not operate (at this time, the original signal is removed). During the entire operation, the BTB line corresponding to the "on" and empty chassis controller remains in the "0" state, and the BTL line corresponding to the unconnected chassis controller remains in the "1" state. During each stage, the timing signal sequence is automatically adjusted to adapt to the actual signal delay occurring on the branch information road and the response time required by the chassis controller. The timing of the
command mode operation is described in Section 3.1 [Details are also provided; the classification and operation standards are described in Section 5.2. In practice, the transmission delay of the data of the branch is different. This signal offset problem is described in Section 5.3. If the branch driver or the addressed chassis controller cannot respond to the timing signal in the specified sequence, the branch operation cannot be completed. Therefore, the branch driver should be equipped with some form of timeout device to detect the situation where the operation fails to be completed within a specified time so that appropriate adjustments can be made. To prevent operation errors caused by missing or offline chassis controllers, the relevant methods described in Section 5.4 can be used.
The relationship between the branch information path operation and the chassis data path operation of the chassis 5 to be detected must meet the requirements of Table 3 and GB5691--85.
The timing relationship between the chassis data selection signals (S1 and S2) and the branch timing signals (BTA and BTB) is specified in detail in the A1 chassis controller (see Section A.7). In other chassis controllers, this timing relationship will depend on whether there are registers for commands and data.
5.1 Command mode operation
The timing of command mode operation is shown in Table 3.
The following sections describe the stages of a read operation and explain the differences between other operations and read operations. In any operation, one or more chassis may be disconnected. 5.1.1 Read operation: Reading section 1 (function 7) timing diagram 3 [.
B(CR.NAF)
its timing
(internal delay-
GB 5693-85
branch operation
earliest
lastearliest
chassis data path operation
Figure 3 branch read operation preparation
next branch connection part
action in bd
verification delay
action in cciFrom the branch information road
BQ and BX
(and read data)
During the whole operation, BG=0
When the command is required, the action shown in the brackets is executed
GB 5693-85
Stage 1, the branch driver sends a branch command (including write data when writing command) or a hierarchical query (BG) and the corresponding right box address (BCR) at its end. After compensating the delay of the sign deviation, it generates BTA-1 and starts the next stage. Section 2, each chassis controller that is addressed responds to A=1. When operating in command mode, the chassis controller starts the chassis data path operation and establishes Q, X and some read data at its port; when operating in hierarchical L mode, hierarchical L information is established at its port. Then BTB:=0 is generated on its BTB dedicated line. Only when the branch driver receives BTB=0 from all addressed chassis controllers, it starts a stage of operation. In stage 3, the branch driver enters a period of time to compensate for the number shift, and then receives Q, X and read data or level L information. It generates BTA=0 and starts the next stage of operation.
In stage 4, each addressed chassis controller responds to BTA=0. In command mode operation, it ends the chassis data transmission operation and removes Q, X and read data at its port. In level operation, it removes level L information at its port. Then its BTB dedicated line generates BTR:=1:
When the branch driver receives BTB=1 from all addressed chassis controllers, it ends stage 4. After that, it can start another branch operation (constructing a new command, writing data or level query signal), or it can temporarily not operate (at this time, the original signal is removed). During the entire operation, the BTB line corresponding to the "on" and empty chassis controller remains in the "0" state, and the BTL line corresponding to the unconnected chassis controller remains in the "1" state. During each stage, the timing signal sequence is automatically adjusted to adapt to the actual signal delay occurring on the branch information road and the response time required by the chassis controller. The timing of the
command mode operation is described in Section 3.1 [Details are also provided; the classification and operation standards are described in Section 5.2. In practice, the transmission delay of the data of the branch is different. This signal offset problem is described in Section 5.3. If the branch driver or the addressed chassis controller cannot respond to the timing signal in the specified sequence, the branch operation cannot be completed. Therefore, the branch driver should be equipped with some form of timeout device to detect the situation where the operation fails to be completed within a specified time so that appropriate adjustments can be made. To prevent operation errors caused by missing or offline chassis controllers, the relevant methods described in Section 5.4 can be used.
The relationship between the branch information path operation and the chassis data path operation of the chassis 5 to be detected must meet the requirements of Table 3 and GB5691--85.
The timing relationship between the chassis data selection signals (S1 and S2) and the branch timing signals (BTA and BTB) is specified in detail in the A1 chassis controller (see Section A.7). In other chassis controllers, this timing relationship will depend on whether there are registers for commands and data.
5.1 Command mode operation
The timing of command mode operation is shown in Table 3.
The following sections describe the stages of a read operation and explain the differences between other operations and read operations. In any operation, one or more chassis may be disconnected. 5.1.1 Read operation: Reading section 1 (function 7) timing diagram 3 [.
B(CR.NAF)
its timing
(internal delay-
GB 5693-85
branch operation
earliest
lastearliest
chassis data path operation
Figure 3 branch read operation preparation
next branch connection part
action in bd
verification delay
action in cci
Tip: This standard content only shows part of the intercepted content of the complete standard. If you need the complete standard, please go to the top to download the complete standard document for free.